View MKE02P64M40SF0_9077463.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MKE02P64M40SF0 ke02 sub-family data sheet supports the following: mke02z16vlc4(r), mke02z32vlc4(r), mke02z64vlc4(r), mke02z16vld4(r), mke02z32vld4(r), mke02z64vld4(r), mke02z32vlh4(r), mke02z64vlh4(r), mke02z32vqh4(r), mke02z64vqh4(r), mke02z16vfm4(r), mke02z32vfm4(r), and mke02z64vfm4(r) key features ? operating characteristics C voltage range: 2.7 to 5.5 v C flash write voltage range: 2.7 to 5.5 v C temperature range (ambient): -40 to 105c ? performance C up to 40 mhz arm? cortex-m0+ core and up to 20 mhz bus clock C single cycle 32-bit x 32-bit multiplier C single cycle i/o access port ? memories and memory interfaces C up to 64 kb flash C up to 256 b eeprom C up to 4 kb ram ? clocks C oscillator (osc) - supports 32.768 khz crystal or 4 mhz to 20 mhz crystal or ceramic resonator; choice of low power or high gain oscillators C internal clock source (ics) - internal fll with internal or external reference, 31.25 khz pre- trimmed internal reference for 32 mhz system clock (able to be trimmed for up to 40 mhz system clock) C internal 1 khz low-power oscillator (lpo) ? system peripherals C power management module (pmc) with three power modes: run, wait, stop C low-voltage detection (lvd) with reset or interrupt, selectable trip points C watchdog with independent clock source (wdog) C programmable cyclic redundancy check module (crc) C serial wire debug interface (swd) C bit manipulation engine (bme) ? security and integrity modules C 64-bit unique identification (id) number per chip ? human-machine interface C up to 57 general-purpose input/output (gpio) C two up to 8-bit keyboard interrupt modules (kbi) C external interrupt (irq) ? analog modules C one up to 16-channel 12-bit sar adc, operation in stop mode, optional hardware trigger (adc) C two analog comparators containing a 6-bit dac and programmable reference input (acmp) nxp semiconductors document number MKE02P64M40SF0 data sheet: technical data rev. 4, 07/2016 nxp reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
? timers C one 6-channel flextimer/pwm (ftm) C two 2-channel flextimer/pwm (ftm) C one 2-channel periodic interrupt timer (pit) C one real-time clock (rtc) ? communication interfaces C two spi modules (spi) C up to three uart modules (uart) C one i2c module (i2c) ? package options C 64-pin qfp/lqfp C 44-pin lqfp C 32-pin lqfp C 32-pin qfn ke02 sub-family data sheet, rev. 4, 07/2016 2 nxp semiconductors
table of contents 1 ordering parts....................................................................................... 4 1.1 determining valid orderable parts............................................... 4 2 part identification................................................................................. 4 2.1 description................................................................................... 4 2.2 format.......................................................................................... 4 2.3 fields............................................................................................ 4 2.4 example....................................................................................... 5 3 parameter classification........................................................................ 5 4 ratings.................................................................................................. 6 4.1 thermal handling ratings............................................................. 6 4.2 moisture handling ratings............................................................ 6 4.3 esd handling ratings................................................................... 6 4.4 voltage and current operating ratings.......................................... 7 5 general................................................................................................. 7 5.1 nonswitching electrical specifications........................................ 7 5.1.1 dc characteristics.......................................................... 7 5.1.2 supply current characteristics........................................ 14 5.1.3 emc performance.......................................................... 15 5.2 switching specifications.............................................................. 16 5.2.1 control timing................................................................ 16 5.2.2 ftm module timing....................................................... 17 5.3 thermal specifications................................................................. 18 5.3.1 thermal operating requirements.................................... 18 5.3.2 thermal characteristics.................................................. 19 6 peripheral operating requirements and behaviors................................ 20 6.1 core modules............................................................................... 20 6.1.1 swd electricals ............................................................. 20 6.2 external oscillator (osc) and ics characteristics....................... 21 6.3 nvm specifications..................................................................... 23 6.4 analog.......................................................................................... 24 6.4.1 adc characteristics....................................................... 25 6.4.2 analog comparator (acmp) electricals......................... 27 6.5 communication interfaces........................................................... 28 6.5.1 spi switching specifications.......................................... 28 7 dimensions........................................................................................... 31 7.1 obtaining package dimensions.................................................... 31 8 pinout................................................................................................... 32 8.1 signal multiplexing and pin assignments.................................... 32 8.2 device pin assignment................................................................. 34 9 revision history.................................................................................... 36 ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 3
ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: ke02z. part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q ke## a fff r t pp cc n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification ke## kinetis family ? ke02 a key attribute ? z = m0+ core fff program flash memory size ? 16 = 16 kb ? 32 = 32 kb ? 64 = 64 kb r silicon revision ? (blank) = main ? a = revision after main table continues on the next page... 1 2 ordering parts ke02 sub-family data sheet, rev. 4, 07/2016 4 nxp semiconductors
field description values t temperature range (c) ? v = C40 to 105 pp package identifier ? lc = 32 lqfp (7 mm x 7 mm) ? fm = 32 qfn (5 mm x 5 mm) ? ld = 44 lqfp (10 mm x 10 mm) ? qh = 64 qfp (14 mm x 14 mm) ? lh = 64 lqfp (10 mm x 10 mm) cc maximum cpu frequency (mhz) ? 4 = 40 mhz n packaging type ? r = tape and reel ? (blank) = trays 2.4 example this is an example part number: mke02z64vqh4 3 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: table 1. parameter classifications p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. note the classification is shown in the column labeled c in the parameter tables where appropriate. parameter classification ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 5
ratings 4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 4.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 4.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model C6000 +6000 v 1 v cdm electrostatic discharge voltage, charged-device model C500 +500 v 2 i lat latch-up current at ambient temperature of 125c C100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 3. determined according to jedec standard jesd78d, ic latch-up test . ? test was performed at 125 c case temperature (class ii). ? i/o pins pass 100 ma i-test with i dd current limit at 800 ma. ? i/o pins pass +60/-100 ma i-test with i dd current limit at 1000 ma. ? supply groups pass 1.5 v ccmax . ? reset pin was only tested with negative i-test due to product conditioning requirement. 4 ratings ke02 sub-family data sheet, rev. 4, 07/2016 6 nxp semiconductors
4.4 voltage and current operating ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified in the following table may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this document. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ) or the programmable pullup resistor associated with the pin is enabled. table 2. voltage and current operating ratings symbol description min. max. unit v dd digital supply voltage C0.3 6.0 v i dd maximum current into v dd 120 ma v in input voltage except true open drain pins C0.3 v dd + 0.3 1 v input voltage of true open drain pins C0.3 6 v i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v 1. maximum rating of v dd also applies to v in . general nonswitching electrical specifications 5.1.1 dc characteristics this section includes information about power supply requirements and i/o pin characteristics. table 3. dc characteristics symbol c descriptions min typical 1 max unit operating voltage 2.7 5.5 v table continues on the next page... 5 5.1 general ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 7
table 3. dc characteristics (continued) symbol c descriptions min typical 1 max unit v oh p output high voltage all i/o pins, except pta2 and pta3, standard- drive strength 5 v, i load = C5 ma v dd C 0.8 v c 3 v, i load = C2.5 ma v dd C 0.8 v p high current drive pins, high-drive strength 2 5 v, i load = C20 ma v dd C 0.8 v c 3 v, i load = C10 ma v dd C 0.8 v i oht d output high current max total i oh for all ports 5 v C100 ma 3 v C60 v ol p output low voltage all i/o pins, standard- drive strength 5 v, i load = 5 ma 0.8 v c 3 v, i load = 2.5 ma 0.8 v p high current drive pins, high-drive strength 2 5 v, i load =20 ma 0.8 v c 3 v, i load = 10 ma 0.8 v i olt d output low current max total i ol for all ports 5 v 100 ma 3 v 60 v ih p input high voltage all digital inputs 4.5v dd <5.5 v 0.65 v dd v 2.7v dd <4.5 v 0.70 v dd v il p input low voltage all digital inputs 4.5v dd <5.5 v 0.35 v dd v 2.7v dd <4.5 v 0.30 v dd v hys c input hysteresi s all digital inputs 0.06 v dd mv |i in | p input leakage current per pin (pins in high impedance input mode) v in = v dd or v ss 0.1 1 a |i intot | c total leakage combine d for all port pins pins in high impedance input mode v in = v dd or v ss 2 a r pu p pullup resistors all digital inputs, when enabled (all i/o pins other than pta2 and pta3) 30.0 50.0 k? r pu 3 p pullup resistors pta2 and pta3 pins 30.0 60.0 k? i ic d dc injection current 4 , 5 , 6 single pin limit v in < v ss , v in > v dd -2 2 ma total mcu limit, includes sum of all stressed pins -5 25 c in c input capacitance, all pins 7 pf v ram c ram retention voltage 2.0 v 1. typical values are measured at 25 c. characterized, not tested. 2. only ptb4, ptb5, ptd0, ptd1, pte0, pte1, pth0, and pth1 support high current output. nonswitching electrical specifications ke02 sub-family data sheet, rev. 4, 07/2016 8 nxp semiconductors
3. the specified resistor value is the actual value internal to the device. the pullup value may appear higher when measured externally on the pin. 4. all functional non-supply pins, except for pta2 and pta3, are internally clamped to v ss and v dd . pta2 and pta3 are true open drain i/o pins that are internally clamped to v ss . 5. input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger value. 6. power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if the positive injection current (v in > v dd ) is higher than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure that external v dd load will shunt current higher than maximum injection current when the mcu is not consuming power, such as when no system clock is present, or clock rate is very low (which would reduce overall power consumption). table 4. lvd and por specification symbol c description min typ max unit v por d por re-arm voltage 1 1.5 1.75 2.0 v v lvdh c falling low-voltage detect thresholdhigh range (lvdv = 1) 2 4.2 4.3 4.4 v v lvw1h c falling low- voltage warning threshold high range level 1 falling (lvwv = 00) 4.3 4.4 4.5 v v lvw2h c level 2 falling (lvwv = 01) 4.5 4.5 4.6 v v lvw3h c level 3 falling (lvwv = 10) 4.6 4.6 4.7 v v lvw4h c level 4 falling (lvwv = 11) 4.7 4.7 4.8 v v hysh c high range low-voltage detect/warning hysteresis 100 mv v lvdl c falling low-voltage detect thresholdlow range (lvdv = 0) 2.56 2.61 2.66 v v lvw1l c falling low- voltage warning threshold low range level 1 falling (lvwv = 00) 2.62 2.7 2.78 v v lvw2l c level 2 falling (lvwv = 01) 2.72 2.8 2.88 v v lvw3l c level 3 falling (lvwv = 10) 2.82 2.9 2.98 v v lvw4l c level 4 falling (lvwv = 11) 2.92 3.0 3.08 v v hysdl c low range low-voltage detect hysteresis 40 mv v hyswl c low range low-voltage warning hysteresis 80 mv v bg p buffered bandgap output 3 1.14 1.16 1.18 v 1. maximum is highest voltage that por is guaranteed. 2. rising thresholds are falling threshold + hysteresis. 3. voltage factory trimmed at v dd = 5.0 v, temp = 25 c nonswitching electrical specifications ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 9
i oh (ma) v dd -v oh (v) figure 1. typical v dd -v oh vs. i oh (standard drive strength) (v dd = 5 v) i oh (ma) v dd -v oh (v) figure 2. typical v dd -v oh vs. i oh (standard drive strength) (v dd = 3 v) nonswitching electrical specifications ke02 sub-family data sheet, rev. 4, 07/2016 10 nxp semiconductors
i oh ( ma ) v dd - v oh (v) figure 3. typical v dd -v oh vs. i oh (high drive strength) (v dd = 5 v) i oh (ma) v dd -v oh (v) figure 4. typical v dd -v oh vs. i oh (high drive strength) (v dd = 3 v) nonswitching electrical specifications ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 11
i ol ( ma ) v ol (v) figure 5. typical v ol vs. i ol (standard drive strength) (v dd = 5 v) i ol ( ma ) v ol (v) figure 6. typical v ol vs. i ol (standard drive strength) (v dd = 3 v) nonswitching electrical specifications ke02 sub-family data sheet, rev. 4, 07/2016 12 nxp semiconductors
i ol ( ma ) v ol (v) figure 7. typical v ol vs. i ol (high drive strength) (v dd = 5 v) i ol ( ma ) v ol (v) figure 8. typical v ol vs. i ol (high drive strength) (v dd = 3 v) nonswitching electrical specifications ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 13
5.1.2 supply current characteristics this section includes information about power supply current in various operating modes. table 5. supply current characteristics c parameter symbol core/bus freq v dd (v) typical 1 max 2 unit temp c run supply current fei mode, all modules clocks enabled; run from flash ri dd 40/20 mhz 5 7.8 ma C40 to 105 c c 20/20 mhz 6.7 c 10/10 mhz 4.5 1/1 mhz 1.5 c 40/20 mhz 3 7.7 c 20/20 mhz 6.6 c 10/10 mhz 4.4 1/1 mhz 1.45 c run supply current fei mode, all modules clocks disabled; run from flash ri dd 40/20 mhz 5 6.3 ma C40 to 105 c c 20/20 mhz 5.3 c 10/10 mhz 3.7 1/1 mhz 1.5 c 40/20 mhz 3 6.2 c 20/20 mhz 5.3 c 10/10 mhz 3.7 1/1 mhz 1.4 c run supply current fbe mode, all modules clocks enabled; run from ram ri dd 40/20 mhz 5 10.3 ma C40 to 105 c p 20/20 mhz 9 14.8 c 10/10 mhz 5.2 1/1 mhz 1.45 c 40/20 mhz 3 10.2 p 20/20 mhz 8.8 11.8 c 10/10 mhz 5.1 1/1 mhz 1.4 c run supply current fbe mode, all modules clocks disabled; run from ram ri dd 40/20 mhz 5 8.9 ma C40 to 105 c p 20/20 mhz 8 12.3 c 10/10 mhz 4.4 1/1 mhz 1.35 c 40/20 mhz 3 8.8 p 20/20 mhz 7.8 9.2 c 10/10 mhz 4.2 1/1 mhz 1.3 table continues on the next page... nonswitching electrical specifications ke02 sub-family data sheet, rev. 4, 07/2016 14 nxp semiconductors
table 5. supply current characteristics (continued) c parameter symbol core/bus freq v dd (v) typical 1 max 2 unit temp c wait mode current fei mode, all modules clocks enabled wi dd 40/20 mhz 5 6.4 ma C40 to 105 c p 20/20 mhz 5.5 c 20/10 mhz 3.5 1/1 mhz 1.4 c 40/20 mhz 3 6.3 c 20/20 mhz 5.4 10/10 mhz 3.4 1/1 mhz 1.4 p stop mode supply current no clocks active (except 1 khz lpo clock) 3 si dd 5 2 85 a C40 to 105 c p 3 1.9 80 C40 to 105 c c adc adder to stop adlpc = 1 adlsmp = 1 adco = 1 mode = 10b adiclk = 11b 5 86 (64-, 44- pin packages) 42 (32-pin package) a C40 to 105 c c 3 82 (64-, 44- pin packages) 41 (32-pin package) c acmp adder to stop 5 12 a C40 to 105 c c 3 12 c lvd adder to stop 4 5 128 a C40 to 105 c c 3 124 1. data in typical column was characterized at 5.0 v, 25 c or is typical recommended value. 2. the max current is observed at high temperature of 105 c. 3. rtc adder causes i dd to increase typically by less than 1 a; rtc clock source is 1 khz lpo clock. 4. lvd is periodically woken up from stop by 5% duty cycle. the period is equal to or less than 2 ms. 5.1.3 emc performance electromagnetic compatibility (emc) performance is highly dependent on the environment in which the mcu resides. board design and layout, circuit topology choices, location and characteristics of external components as well as mcu software operation play a significant role in emc performance. the system designer must consult the following applications notes, available on nxp.com for advice and guidance specifically targeted at optimizing emc performance. ? an2321: designing for board level electromagnetic compatibility ? an1050: designing for electromagnetic compatibility (emc) with hcmos microcontrollers nonswitching electrical specifications ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 15
? an1263: designing for electromagnetic compatibility with single-chip microcontrollers ? an2764: improving the transient immunity performance of microcontroller-based applications ? an1259: system design and layout techniques for noise reduction in mcu- based systems 5.1.3.1 emc radiated emissions operating behaviors table 6. emc radiated emissions operating behaviors for 64-pin qfp package symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 14 dbv 1 , 2 v re2 radiated emissions voltage, band 2 50C150 15 dbv v re3 radiated emissions voltage, band 3 150C500 3 dbv v re4 radiated emissions voltage, band 4 500C1000 4 dbv v re_iec iec level 0.15C1000 m 2 , 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 61967-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . measurements were made while the microcontroller was running basic application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. v dd = 5.0 v, t a = 25 c, f osc = 10 mhz (crystal), f bus = 20 mhz 3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method switching specifications 5.2.1 control timing table 7. control timing num c rating symbol min typical 1 max unit 1 d system and core clock f sys dc 40 mhz 2 p bus frequency (t cyc = 1/f bus ) f bus dc 20 mhz 3 p internal low power oscillator frequency f lpo 0.67 1.0 1.25 khz 4 d external reset pulse width 2 t extrst 1.5 t cyc ns 5 d reset low drive t rstdrv 34 t cyc ns 6 d irq pulse width asynchronous path 2 t ilih 100 ns d synchronous path 3 t ihil 1.5 t cyc ns table continues on the next page... 5.2 switching specifications ke02 sub-family data sheet, rev. 4, 07/2016 16 nxp semiconductors
table 7. control timing (continued) num c rating symbol min typical 1 max unit 7 d keyboard interrupt pulse width asynchronous path 2 t ilih 100 ns d synchronous path t ihil 1.5 t cyc ns 8 c port rise and fall time - normal drive strength (load = 50 pf) 4 t rise 10.2 ns c t fall 9.5 ns c port rise and fall time - high drive strength (load = 50 pf) 4 t rise 5.4 ns c t fall 4.6 ns 1. typical values are based on characterization data at v dd = 5.0 v, 25 c unless otherwise stated. 2. this is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 4. timing is shown with respect to 20% v dd and 80% v dd levels. temperature range -40 c to 105 c. ? ? ? ? ? ? ? ? t extrst reset_b pin figure 9. reset timing t ihil kbipx t ilih irq /kbipx figure 10. kbipx timing 5.2.2 ftm module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. table 8. ftm input timing c function symbol min max unit d external clock frequency f tclk 0 f bus /4 hz d external clock period t tclk 4 t cyc table continues on the next page... switching specifications ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 17
table 8. ftm input timing (continued) c function symbol min max unit d external clock high time t clkh 1.5 t cyc d external clock low time t clkl 1.5 t cyc d input capture pulse width t icpw 1.5 t cyc ? ? ? ? ? ? ? ? t tclk t clkh t clkl tclk figure 11. timer external clock ? ? ? ? ? ? ? ? t icpw ftmchn t icpw ftmchn figure 12. timer input capture pulse thermal specifications 5.3.1 thermal operating requirements table 9. thermal operating requirements symbol description min. max. unit notes t j die junction temperature C40 125 c t a ambient temperature C40 105 c 1 1. maximum t a can be exceeded only if the user ensures that t j does not exceed maximum t j . the simplest method to determine t j is: t j = t a + ja x chip power dissipation 5.3 thermal specifications ke02 sub-family data sheet, rev. 4, 07/2016 18 nxp semiconductors
5.3.2 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user- determined rather than being controlled by the mcu design. to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. table 10. thermal attributes board type symbo l description 64 lqfp 64 qfp 44 lqfp 32 lqfp 32 qfn unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 71 61 75 86 97 c/w 1 , 2 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 53 47 53 57 33 c/w 1 , 3 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) 59 50 62 72 81 c/w 1 , 3 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) 46 41 47 51 27 c/w 1 , 3 r jb thermal resistance, junction to board 35 32 34 33 12 c/w 4 r jc thermal resistance, junction to case 20 23 20 24 1.3 c/w 5 jt thermal characterization parameter, junction to package top outside center (natural convection) 5 8 5 6 3 c/w 6 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per jedec jesd51-2 with the single layer board (jesd51-3) horizontal. 3. per jedec jesd51-6 with the board (jesd51-7) horizontal. 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the solder pad on the bottom of the package. interface resistance is ignored. 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization. the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) thermal specifications ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 19
where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts - chip internal power p i/o = power dissipation on input and output pins - user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) solving the equations above for k gives: k = p d (t a + 273 c) + ja (p d ) 2 where k is a constant pertaining to the particular part. k can be determined by measuring p d (at equilibrium) for an known t a . using this value of k, the values of p d and t j can be obtained by solving the above equations iteratively for any value of t a . 6 peripheral operating requirements and behaviors 6.1 core modules 6.1.1 swd electricals table 11. swd full voltage range electricals symbol description min. max. unit operating voltage 2.7 5.5 v j1 swd_clk frequency of operation ? serial wire debug 0 20 mhz j2 swd_clk cycle period 1/j1 ns j3 swd_clk clock pulse width ? serial wire debug 20 ns j4 swd_clk rise and fall times 3 ns j9 swd_dio input data setup time to swd_clk rise 10 ns j10 swd_dio input data hold time after swd_clk rise 3 ns table continues on the next page... peripheral operating requirements and behaviors ke02 sub-family data sheet, rev. 4, 07/2016 20 nxp semiconductors
table 11. swd full voltage range electricals (continued) symbol description min. max. unit j11 swd_clk high to swd_dio data valid 35 ns j12 swd_clk high to swd_dio high-z 5 ns j2 j3 j3 j4 j4 swd_clk (input) figure 13. serial wire clock input timing j11 j12 j11 j9 j10 input data valid output data valid output data valid swd_clk swd_dio swd_dio swd_dio swd_dio figure 14. serial wire data timing 6.2 external oscillator (osc) and ics characteristics table 12. osc and ics specifications (temperature range = -40 to 105 c ambient) num c characteristic symbol min typical 1 max unit 1 c crystal or resonator frequency low range (range = 0) f lo 31.25 32.768 39.0625 khz c high range (range = 1) f hi 4 20 mhz table continues on the next page... peripheral operating requirements and behaviors ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 21
table 12. osc and ics specifications (temperature range = -40 to 105 c ambient) (continued) num c characteristic symbol min typical 1 max unit 2 d load capacitors c1, c2 see note 2 3 d feedback resistor low frequency, low-power mode 3 r f m? low frequency, high-gain mode 10 m? high frequency, low- power mode 1 m? high frequency, high-gain mode 1 m? 4 d series resistor - low frequency low-power mode 3 r s 0 k? high-gain mode 200 k? 5 d series resistor - high frequency low-power mode 3 r s 0 k? d series resistor - high frequency, high-gain mode 4 mhz 0 k? d 8 mhz 0 k? d 16 mhz 0 k? 6 c crystal start-up time low range = 32.768 khz crystal; high range = 20 mhz crystal 4 , 5 low range, low power t cstl 1000 ms c low range, high gain 800 ms c high range, low power t csth 3 ms c high range, high gain 1.5 ms 7 t internal reference start-up time t irst 20 50 s 8 p internal reference clock (irc) frequency trim range f int_t 31.25 39.0625 khz 9 p internal reference clock frequency, factory trimmed , t = 25 c, v dd = 5 v f int_ft 31.25 khz 10 p dco output frequency range fll reference = fint_t, flo, or fhi/rdiv f dco 32 40 mhz 11 p factory trimmed internal oscillator accuracy t = 25 c, v dd = 5 v f int_ft -0.5 0.5 % 12 c deviation of irc over temperature when trimmed at t = 25 c, v dd = 5 v over temperature range from -40 c to 105c f int_t -1 0.5 % over temperature range from 0 c to 105c f int_t -0.5 0.5 13 c frequency accuracy of dco output using factory trim value over temperature range from -40 c to 105c f dco_ft -1.5 1 % over temperature range from 0 c to 105c f dco_ft -1 1 table continues on the next page... peripheral operating requirements and behaviors ke02 sub-family data sheet, rev. 4, 07/2016 22 nxp semiconductors
table 12. osc and ics specifications (temperature range = -40 to 105 c ambient) (continued) num c characteristic symbol min typical 1 max unit 14 c fll acquisition time 4 , 6 t acquire 2 ms 15 c long term jitter of dco output clock (averaged over 2 ms interval) 7 c jitter 0.02 0.2 %f dco 1. data in typical column was characterized at 5.0 v, 25 c or is typical recommended value. 2. see crystal or resonator manufacturer's recommendation. 3. load capacitors (c 1 ,c 2 ), feedback resistor (r f ) and series resistor (r s ) are incorporated internally when range = hgo = 0. 4. this parameter is characterized and not tested on each device. 5. proper pc board layout procedures must be followed to achieve specifications. 6. this specification applies to any time the fll reference source or reference divider is changed, trim value changed, or changing from fll disabled (fbelp, fbilp) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f bus . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. osc extal crystal or resonator r s c 2 r f c 1 xtal figure 15. typical crystal or resonator circuit 6.3 nvm specifications this section provides details about program/erase times and program/erase endurance for the flash and eeprom memories. table 13. flash and eeprom characteristics c characteristic symbol min 1 typical 2 max 3 unit 4 d supply voltage for program/erase C40 c to 105 c v prog/erase 2.7 5.5 v d supply voltage for read operation v read 2.7 5.5 v table continues on the next page... peripheral operating requirements and behaviors ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 23
table 13. flash and eeprom characteristics (continued) c characteristic symbol min 1 typical 2 max 3 unit 4 d nvm bus frequency f nvmbus 1 25 mhz d nvm operating frequency f nvmop 0.8 1 1.05 mhz d erase verify all blocks t vfyall 17338 t cyc d erase verify flash block t rd1blk 16913 t cyc d erase verify eeprom block t rd1blk 810 t cyc d erase verify flash section t rd1sec 484 t cyc d erase verify eeprom section t drd1sec 555 t cyc d read once t rdonce 450 t cyc d program flash (2 word) t pgm2 0.12 0.12 0.29 ms d program flash (4 word) t pgm4 0.20 0.21 0.46 ms d program once t pgmonce 0.20 0.21 0.21 ms d program eeprom (1 byte) t dpgm1 0.10 0.10 0.27 ms d program eeprom (2 byte) t dpgm2 0.17 0.18 0.43 ms d program eeprom (3 byte) t dpgm3 0.25 0.26 0.60 ms d program eeprom (4 byte) t dpgm4 0.32 0.33 0.77 ms d erase all blocks t ersall 96.01 100.78 101.49 ms d erase flash block t ersblk 95.98 100.75 101.44 ms d erase flash sector t erspg 19.10 20.05 20.08 ms d erase eeprom sector t derspg 4.81 5.05 20.57 ms d unsecure flash t unsecu 96.01 100.78 101.48 ms d verify backdoor access key t vfykey 464 t cyc d set user margin level t mloadu 407 t cyc c flash program/erase endurance t l to t h = -40 c to 105 c n flpe 10 k 100 k cycles c eeprom program/erase endurance tl to th = -40 c to 105 c n flpe 50 k 500 k cycles c data retention at an average junction temperature of t javg = 85c after up to 10,000 program/erase cycles t d_ret 15 100 years 1. minimum times are based on maximum f nvmop and maximum f nvmbus 2. typical times are based on typical f nvmop and maximum f nvmbus 3. maximum times are based on typical f nvmop and typical f nvmbus plus aging 4. t cyc = 1 / f nvmbus program and erase operations do not require any special power sources other than the normal v dd supply. for more detailed information about program/erase operations, see the flash memory module section in the reference manual. peripheral operating requirements and behaviors ke02 sub-family data sheet, rev. 4, 07/2016 24 nxp semiconductors
6.4 analog 6.4.1 adc characteristics table 14. 5 v 12-bit adc operating conditions characteri stic conditions symbol min typ 1 max unit comment reference potential ? low ? high v refl v refh v ssa v dda v ssa v dda v supply voltage absolute v dda 2.7 5.5 v delta to v dd (v dd -v dda ) v dda -100 0 +100 mv ground voltage delta to v ss (v ss -v ssa ) v ssa -100 0 +100 mv input voltage v adin v refl v refh v input capacitance c adin 4.5 5.5 pf input resistance r adin 3 5 k? analog source resistance 12-bit mode ? f adck > 4 mhz ? f adck < 4 mhz r as 2 5 k? external to mcu 10-bit mode ? f adck > 4 mhz ? f adck < 4 mhz 5 10 8-bit mode (all valid f adck ) 10 adc conversion clock frequency high speed (adlpc=0) f adck 0.4 8.0 mhz low power (adlpc=1) 0.4 4.0 1. typical values assume v dda = 5.0 v, temp = 25c, f adck =1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. peripheral operating requirements and behaviors ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 25
adc sar engine simplified channel select circuit simplified input pin equivalent circuit pad leakage due to input protection z as r as c as v adin v as z adin r adin r adin r adin r adin input pin input pin input pin c adin figure 16. adc input impedance equivalency diagram table 15. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) characteristic conditions c symbol min typ 1 max unit supply current adlpc = 1 adlsmp = 1 adco = 1 t i dda 133 a supply current adlpc = 1 adlsmp = 0 adco = 1 t i dda 218 a supply current adlpc = 0 adlsmp = 1 adco = 1 t i dda 327 a supply current adlpc = 0 adlsmp = 0 adco = 1 t i dda 582 990 a supply current stop, reset, module off t i dda 0.011 1 a adc asynchronous clock source high speed (adlpc = 0) p f adack 2 3.3 5 mhz table continues on the next page... peripheral operating requirements and behaviors ke02 sub-family data sheet, rev. 4, 07/2016 26 nxp semiconductors
table 15. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) characteristic conditions c symbol min typ 1 max unit low power (adlpc = 1) 1.25 2 3.3 conversion time (including sample time) short sample (adlsmp = 0) t t adc 20 adck cycles long sample (adlsmp = 1) 40 sample time short sample (adlsmp = 0) t t ads 3.5 adck cycles long sample (adlsmp = 1) 23.5 total unadjusted error 2 12-bit mode 3 t e tue 3.6 lsb 4 10-bit mode p 1.5 2.0 8-bit mode t 0.7 1.0 differential non- liniarity 12-bit mode t dnl 1.0 lsb 4 10-bit mode 5 p 0.25 0.5 8-bit mode 5 t 0.15 0.25 integral non-linearity 12-bit mode 3 t inl 1.0 lsb 4 10-bit mode t 0.3 0.5 8-bit mode t 0.15 0.25 zero-scale error 6 12-bit mode c e zs 2.0 lsb 4 10-bit mode p 0.25 1.0 8-bit mode t 0.65 1.0 full-scale error 7 12-bit mode t e fs 2.5 lsb 4 10-bit mode t 0.5 1.0 8-bit mode t 0.5 1.0 quantization error 12 bit modes d e q 0.5 lsb 4 input leakage error 8 all modes d e il i in * r as mv temp sensor slope -40 cC25 c d m 3.266 mv/c 25 cC125 c 3.638 temp sensor voltage 25 c d v temp25 1.396 v 1. typical values assume v dda = 5.0 v, temp = 25 c, f adck =1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. includes quantization 3. this parameter is valid for the temperature range of 25 c to 50 c. 4. 1 lsb = (v refh - v refl )/2 n 5. monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes 6. v adin = v ssa 7. v adin = v dda 8. i in = leakage current (refer to dc characteristics) peripheral operating requirements and behaviors ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 27
6.4.2 analog comparator (acmp) electricals table 16. comparator electrical specifications c characteristic symbol min typical max unit d supply voltage v dda 2.7 5.5 v t supply current (operation mode) i dda 10 20 a d analog input voltage v ain v ss - 0.3 v dda v p analog input offset voltage v aio 40 mv c analog comparator hysteresis (hyst=0) v h 15 20 mv c analog comparator hysteresis (hyst=1) v h 20 30 mv t supply current (off mode) i ddaoff 60 na c propagation delay t d 0.4 1 s 6.5 communication interfaces 6.5.1 spi switching specifications the serial peripheral interface (spi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the following tables provide timing characteristics for classic spi timing modes. see the spi chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. all timing is shown with respect to 20% v dd and 80% v dd , unless noted, and 25 pf load on all spi pins. all timing assumes high-drive strength is enabled for spi output pins. table 17. spi master mode timing nu m. symbol description min. max. unit comment 1 f op frequency of operation f bus /2048 f bus /2 hz f bus is the bus clock 2 t spsck spsck period 2 x t bus 2048 x t bus ns t bus = 1/f bus 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t bus C 30 1024 x t bus ns 6 t su data setup time (inputs) 8 ns 7 t hi data hold time (inputs) 8 ns 8 t v data valid (after spsck edge) 25 ns 9 t ho data hold time (outputs) 20 ns 10 t ri rise time input t bus C 25 ns table continues on the next page... peripheral operating requirements and behaviors ke02 sub-family data sheet, rev. 4, 07/2016 28 nxp semiconductors
table 17. spi master mode timing (continued) nu m. symbol description min. max. unit comment t fi fall time input 11 t ro rise time output 25 ns t fo fall time output (output) 2 8 6 7 msb in 2 lsb in msb out 2 lsb out 9 5 5 3 (cpol=0) 4 11 11 10 10 spsck spsck (cpol=1) 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. if configured as an output. ss 1 (output) (output) mosi (output) miso (input) bit 6 . . . 1 bit 6 . . . 1 figure 17. spi master mode timing (cpha=0) <> <> 38 2 6 7 msb in 2 bit 6 . . . 1 master msb out 2 master lsb out 5 5 8 10 11 port data port data 3 10 11 4 1.if configured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 9 (output) (cpol=0) spsck spsck (cpol=1) ss 1 (output) (output) mosi (output) miso (input) lsb in bit 6 . . . 1 figure 18. spi master mode timing (cpha=1) peripheral operating requirements and behaviors ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 29
table 18. spi slave mode timing nu m. symbol description min. max. unit comment 1 f op frequency of operation 0 f bus /4 hz f bus is the bus clock as defined in control timing . 2 t spsck spsck period 4 x t bus ns t bus = 1/f bus 3 t lead enable lead time 1 t bus 4 t lag enable lag time 1 t bus 5 t wspsck clock (spsck) high or low time t bus - 30 ns 6 t su data setup time (inputs) 15 ns 7 t hi data hold time (inputs) 25 ns 8 t a slave access time t bus ns time to data active from high-impedance state 9 t dis slave miso disable time t bus ns hold time to high- impedance state 10 t v data valid (after spsck edge) 25 ns 11 t ho data hold time (outputs) 0 ns 12 t ri rise time input t bus - 25 ns t fi fall time input 13 t ro rise time output 25 ns t fo fall time output 2 10 6 7 msb in bit 6 . . . 1 slave msb slave lsb out 11 5 5 3 8 4 13 note: not defined 12 12 11 see note 13 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) lsb in bit 6 . . . 1 figure 19. spi slave mode timing (cpha = 0) peripheral operating requirements and behaviors ke02 sub-family data sheet, rev. 4, 07/2016 30 nxp semiconductors
2 6 7 msb in bit 6 . . . 1 msb out slave lsb out 5 5 10 12 13 3 12 13 4 slave 8 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) note: not defined 11 lsb in bit 6 . . . 1 figure 20. spi slave mode timing (cpha=1) dimensions 7.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to nxp.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 32-pin lqfp 98ash70029a 32-pin qfn 98asa00473d 44-pin lqfp 98ass23225w 64-pin qfp 98asb42844b 64-pin lqfp 98ass23234w 7 dimensions ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 31
pinout 8.1 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. table 19. pin availability by package pin-count pin number lowest priority <-- --> highest 64-qfp/ lqfp 44-lqfp 32- lqfp/qfn port pin alt 1 alt 2 alt 3 alt 4 1 1 1 ptd1 1 kbi1_p1 ftm2_ch3 spi1_mosi 2 2 2 ptd0 1 kbi1_p0 ftm2_ch2 spi1_sck 3 pth7 4 pth6 5 3 pte7 ftm2_clk ftm1_ch1 6 4 pth2 busout ftm1_ch0 7 5 3 vdd 8 6 4 vdda vrefh 2 9 7 5 vrefl 10 8 6 vssa vss 3 11 9 7 ptb7 i2c0_scl extal 12 10 8 ptb6 i2c0_sda xtal 13 11 vss 14 pth1 1 ftm2_ch1 15 pth0 1 ftm2_ch0 16 pte6 17 pte5 18 12 9 ptb5 1 ftm2_ch5 spi0_pcs0 acmp1_out 19 13 10 ptb4 1 ftm2_ch4 spi0_miso nmi acmp1_in2 20 14 11 ptc3 ftm2_ch3 adc0_se11 21 15 12 ptc2 ftm2_ch2 adc0_se10 22 16 ptd7 kbi1_p7 uart2_tx 23 17 ptd6 kbi1_p6 uart2_rx 24 18 ptd5 kbi1_p5 25 19 13 ptc1 ftm2_ch1 adc0_se9 26 20 14 ptc0 ftm2_ch0 adc0_se8 27 ptf7 adc0_se15 table continues on the next page... 8 pinout ke02 sub-family data sheet, rev. 4, 07/2016 32 nxp semiconductors
table 19. pin availability by package pin-count (continued) pin number lowest priority <-- --> highest 64-qfp/ lqfp 44-lqfp 32- lqfp/qfn port pin alt 1 alt 2 alt 3 alt 4 28 ptf6 adc0_se14 29 ptf5 adc0_se13 30 ptf4 adc0_se12 31 21 15 ptb3 kbi0_p7 spi0_mosi ftm0_ch1 adc0_se7 32 22 16 ptb2 kbi0_p6 spi0_sck ftm0_ch0 adc0_se6 33 23 17 ptb1 kbi0_p5 uart0_tx adc0_se5 34 24 18 ptb0 kbi0_p4 uart0_rx adc0_se4 35 ptf3 36 ptf2 37 25 19 pta7 ftm2_flt2 acmp1_in1 adc0_se3 38 26 20 pta6 ftm2_flt1 acmp1_in0 adc0_se2 39 pte4 40 27 vss 41 28 vdd 42 ptf1 43 ptf0 44 29 ptd4 kbi1_p4 45 30 21 ptd3 kbi1_p3 spi1_pcs0 46 31 22 ptd2 kbi1_p2 spi1_miso 47 32 23 pta3 4 kbi0_p3 uart0_tx i2c0_scl 48 33 24 pta2 4 kbi0_p2 uart0_rx i2c0_sda 49 34 25 pta1 kbi0_p1 ftm0_ch1 acmp0_in1 adc0_se1 50 35 26 pta0 kbi0_p0 ftm0_ch0 acmp0_in0 adc0_se0 51 36 27 ptc7 uart1_tx 52 37 28 ptc6 uart1_rx 53 pte3 spi0_pcs0 54 38 pte2 spi0_miso 55 ptg3 56 ptg2 57 ptg1 58 ptg0 59 39 pte1 1 spi0_mosi 60 40 pte0 1 spi0_sck ftm1_clk 61 41 29 ptc5 ftm1_ch1 rtco 62 42 30 ptc4 rtco ftm1_ch0 acmp0_in2 swd_clk 63 43 31 pta5 irq ftm0_clk reset 64 44 32 pta4 acmp0_out swd_dio 1. this is a high-current drive pin when operated as output. pinout ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 33
2. vrefh and vdda are internally connected. 3. vssa and vss are internally connected. 4. this is a true open-drain pin when operated as output. note when an alternative function is first enabled, it is possible to get a spurious edge to the module. user software must clear any associated flags before interrupts are enabled. table 19 illustrates the priority if multiple modules are enabled. the highest priority module will have control over the pin. selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module. disable all modules that share a pin before enabling another module. 8.2 device pin assignment ptf0 ptf2 ptb1 ptb2 ptf6 ptc3 2. true open drain pins pte6 ptg3 ptf1 ptf3 ptb0 ptb3 ptf4 ptf5 ptf7 pta7 pta6 pte4 vss vdd ptd4 ptd3 ptd2 pta3 2 pta2 2 ptg0 ptg2 ptg1 pta1 pta0 ptc7 ptc6 pte3 pte2 pte1 1 pte0 1 ptc5 ptc4 pta5 pta4 ptd1 1 ptd0 1 pth7 pth6 pte7 pth2 vdd vdda/vrefh vrefl vss vssa/vss ptb7 ptb6 pth1 1 pth0 1 pte5 ptb5 1 ptb4 1 ptc2 ptd7 ptd6 ptd5 ptc1 ptc0 1. high source/sink current pins pins in bold are not available on less pin-count packages. 37 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 12 11 13 14 15 16 39 40 38 36 35 34 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 59 58 60 61 62 63 64 figure 21. 64-pin qfp/lqfp packages pinout ke02 sub-family data sheet, rev. 4, 07/2016 34 nxp semiconductors
ptb1 ptb2 ptc3 2. true open drain pins ptb0 ptb3 pta7 pta6 vss vdd ptd4 ptd3 ptd2 pta2 2 pta1 pta0 ptc7 ptc6 pte2 pte1 1 pte0 1 ptc5 ptc4 pta5 pta4 ptd1 1 ptd0 1 pte7 pth2 vdd vdda/vrefh vrefl vss vssa/vss ptb7 ptb6 ptb5 1 ptb4 1 ptc2 ptd7 ptd6 ptd5 ptc1 ptc0 1. high source/sink current pins pins in bold are not available on less pin-count packages. 37 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 12 11 13 14 15 16 39 40 38 36 35 34 33 41 42 43 44 pta3 2 figure 22. 44-pin lqfp package ptb1 ptb2 ptc3 2. true open drain pins ptb0 ptb3 pta7 pta6 ptd3 ptd2 pta2 2 pta1 pta0 ptc7 ptc6 ptc5 ptc4 pta5 pta4 ptd1 1 ptd0 1 vdd vdda/vrefh vrefl vssa/vss ptb7 ptb6 ptb5 1 ptb4 1 ptc2 ptc1 ptc0 1. high source/sink current pins 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 12 11 13 14 15 16 pta3 2 figure 23. 32-pin lqfp package pinout ke02 sub-family data sheet, rev. 4, 07/2016 nxp semiconductors 35
ptb1 ptb2 ptc3 2. true open drain pins ptb0 ptb3 pta7 pta6 ptd3 ptd2 pta2 2 pta1 pta0 ptc7 ptc6 ptc5 ptc4 pta5 pta4 ptd1 1 ptd0 1 vdd vdda/vrefh vrefl vssa/vss ptb7 ptb6 ptb5 1 ptb4 1 ptc2 ptc1 ptc0 1. high source/sink current pins 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 12 11 13 14 15 16 pta3 2 figure 24. 32-pin qfn package 9 revision history the following table provides a revision history for this document. table 20. revision history rev. no. date substantial changes 2 3/2014 initial public release. 3 10/2014 ? added new package of 32-pin qfn information ? updated pin-out ? updated key features of uart, kbi and adc in the front page ? added a note to the max. in supply current characteristics ? updated footnote f osc = 10 mhz (crystal) in emc radiated emissions operating behaviors ? added a new section of thermal operating requirements ? updated nvm specifications ? added reference potential in adc characteristics ? updated to "all timing assumes high-drive strength is enabled for spi output pins." in spi switching specifications 4 07/2016 ? updated the typical value of e tue in 12-bit mode and added a note to the 12-bit mode of e tue and inl in the adc characteristics . revision history ke02 sub-family data sheet, rev. 4, 07/2016 36 nxp semiconductors
how to reach us: home page: nxp.com web support: nxp.com/support information in this document is provided solely to enable system and software implementers to use nxp products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in nxp data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer ? s technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions . nxp, the nxp logo, nxp secure connections for a smarter world, freescale, the freescale logo, and kinetis are trademarks of nxp b.v. all other product or service names are the property of their respective owners. arm, the arm powered logo, and cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. all rights reserved. ?2013-2016 nxp b.v. document number MKE02P64M40SF0 revision 4, 07/2016

▲Up To Search▲

Price & Availability of MKE02P64M40SF0

	To Download MKE02P64M40SF0 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .